RAMMon v1.0 Build: 1002 built with SysInfo v1.0 Build: 1006
PassMark (R) Software
PassMark Software - PC Benchmark and Test Software
Memmory summary for AXEL-PC:
Number of Memory Devices: 2 Total Physical Memory: 2046 MB (2048 MB)
Total Available Physical Memory: 1110 MB
Memory Load: 45%
Item | Slot #1 | Slot #2 | Slot #3 | Slot #4 |
-------------------------------------------------------------------------------|------------------------|------------------------|-----------------|-----------------|-
Ram Type | DDR | DDR | Not Populated | Not Populated |
Standard Name | DDR-400 | DDR-400 | | |
Module Name | PC-3200 | PC-3200 | | |
Memory Capacity (MB) | 1024 | 1024 | | |
Bus Clockspeed (Mhz) | 200.00 | 200.00 | | |
Jedec Manufacture Name | Samsung | Samsung | | |
Search Amazon.com | Search! | Search! | | |
SPD Revision | 0.0 | 0.0 | | |
Registered | No | No | | |
ECC | No | No | | |
DIMM Slot # | 1 | 2 | | |
Manufactured | Week 15 of Year 2006 | Week 15 of Year 2006 | | |
Module Part # | M3 68L2923CUN-CCC | M3 68L2923CUN-CCC | | |
Module Revision | 0x4E43 | 0x4E43 | | |
Module Serial # | 0xF6171AF2 | 0x2D181AF2 | | |
Module Manufacturing Location | 2 | 2 | | |
# of Row Addressing Bits | 13 | 13 | | |
# of Column Addressing Bits | 11 | 11 | | |
# of Banks | 4 | 4 | | |
# of Ranks | 2 | 2 | | |
Device Width in Bits | 8 | 8 | | |
Bus Width in Bits | 64 | 64 | | |
Module Voltage | SSTL 2.5V | SSTL 2.5V | | |
CAS Latencies Supported | 2.5 3.0 | 2.5 3.0 | | |
Timings @ Max Frequency | 3-3-3-8 | 3-3-3-8 | | |
Minimum Clock Cycle Time, tCK (ns) | 5.000 | 5.000 | | |
Minimum CAS Latency Time, tAA (ns) | 15.000 | 15.000 | | |
Minimum RAS to CAS Delay, tRCD (ns) | 15.000 | 15.000 | | |
Minimum Row Precharge Time, tRP (ns) | 15.000 | 15.000 | | |
Minimum Active to Precharge Time, tRAS (ns) | 40.000 | 40.000 | | |
Minimum Row Active to Row Active Delay, tRRD (ns) | 10.000 | 10.000 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Time, tRC (ns) | 55.000 | 55.000 | | |
Minimum Auto-Refresh to Active/Auto-Refresh Command Period, tRFC (ns) | 70.000 | 70.000 | | |
| | | | |
DDR1 Specific SPD Attributes | | | | |
Data Access Time from Clock, tAC (ns) | 0.650 | 0.650 | | |
Clock Cycle Time at Medium CAS Latency (ns) | 6.000 | 6.000 | | |
Data Access Time at Medium CAS Latency (ns) | 0.700 | 0.700 | | |
Clock Cycle Time at Short CAS Latency (ns) | 0.000 | 0.000 | | |
Data Access Time at Short CAS Latency (ns) | 0.000 | 0.000 | | |
Maximum Clock Cycle Time (ns) | 10.000 | 10.000 | | |
Address/Command Setup Time Before Clock, tIS (ns) | 0.600 | 0.600 | | |
Address/Command Hold Time After Clock, tIH (ns) | 0.600 | 0.600 | | |
Data Input Setup Time Before Strobe, tDS (ns) | 0.400 | 0.400 | | |
Data Input Hold Time After Strobe, tDH (ns) | 0.400 | 0.400 | | |
Maximum Skew Between DQS and DQ Signals (ns) | 0.400 | 0.400 | | |
Maximum Read Data hold Skew Factor (ns) | 0.500 | 0.500 | | |
CS Latencies Supported | 0 | 0 | | |
WE Latencies Supported | 1 | 1 | | |
Burst Lengths Supported | 2 4 8 | 2 4 8 | | |
Refresh Rate | Reduced (7.8us) | Reduced (7.8us) | | |
Buffered Address/Control Inputs | No | No | | |
On-card PLL | No | No | | |
FET Switch On-card Enable | No | No | | |
FET Switch External Enable | No | No | | |
Differential Clock Input | Yes | Yes | | |
Weak Driver Included | No | No | | |
Concurrent Auto Precharge Supported | Yes | Yes | | |
Fast AP Supported | Yes | Yes | | |
Module Bank Density | 512 MB | 512 MB | | |
Module Height (mm) | Unavailable | Unavailable | | |