Windows 7 Forums
Welcome to Windows 7 Forums. Our forum is dedicated to helping you find support and solutions for any problems regarding your Windows 7 PC be it Dell, HP, Acer, Asus or a custom build. We also provide an extensive Windows 7 tutorial section that covers a wide range of tips and tricks.


Windows 7: Recurring BSOD Problem


18 Sep 2009   #11

Win7x64
 
 

Quote   Quote: Originally Posted by ssu View Post
Ive only tried the current OS. This computer was built around a month ago, and hasn't been overclocked. Are you saying the hardware is defective, or was it something I did (ive done nothing other than put it together basically)?
I'm 99% confident that your hardware exhibited a defect in 091609-18595-01.dmp. It is virtually impossible to tell (from a minidump) whether the cause is absolutely _broken_ hardware or something like insufficient cooling or a speck of dust lodged in a connector.

Personally, I'd start by running a memory tester for days if necessary - long enough to either find something or convince myself that I'm not going to find unreliable memory using that method.

My System SpecsSystem Spec
.

18 Sep 2009   #12

XP_Pro, W7_7201, W7RC.vhd, SciLinux5.3, Fedora12, Fedora9_2x, OpenSolaris_09-06
 
 

Holy Schmoley!
Real 'computer stuff'!!!

Thanks a million! Your Vista tut looks like a good start point.

DOS Debug in new clothes... (U = Unassemble, etc...)

You got a decent (free) standalone Disassembler to recommend?
Found IDA pro freebie, but ain't looked hard at it yet.

Just wanted to throw a quick reply, to say thanks!
Ditto the extended Memtest, but no CPU exercising there.
MS or Intel or AMD got any hard bangers that you know of?

Ooops, disregard wait -- thought I saw something, but mistaken..
My System SpecsSystem Spec
18 Sep 2009   #13

XP_Pro, W7_7201, W7RC.vhd, SciLinux5.3, Fedora12, Fedora9_2x, OpenSolaris_09-06
 
 

Quote:
fffff880`014e7f4a 48896e20 mov qword ptr [rsi+20h],rbp
fffff880`014e7f4e 48897e08 mov qword ptr [rsi+8],rdi
fffff880`014e7f52 48897e10 mov qword ptr [rsi+10h],rdi
fffff880`014e7f56 48897e18 mov qword ptr [rsi+18h],rdi
The IP seems to count OK:
No instruction at 4b may be because of correct IP increment,
(+1 per byte, viz):
4a = 48 89 6e 20
4b is the '89',
4c is the '6e',
4d is the '20',

then,
4e 48 89 7e 08 <---< is appropriate, count-wise.

What strikes me (as quick first look) is the "Increment" of the
"LOOP" or "REPx" instruction, not proceeding logically:
Starting at +00h, then bumping up by +08h.....

Quote:
Code:

0: kd> u fffff880`014e7f3a
ndis+0x1f3a:
fffff880`014e7f3a 8b6c2430 mov ebp,dword ptr [rsp+30h]
fffff880`014e7f3e 4885f6 test rsi,rsi
fffff880`014e7f41 0f8413840100 je ndis+0x1a35a (fffff880`0150035a)
fffff880`014e7f47 48893e mov qword ptr [rsi],rdi
fffff880`014e7f4a 48896e20 mov qword ptr [rsi+20h],rbp <===< *****
fffff880`014e7f4e 48897e08 mov qword ptr [rsi+8],rdi
fffff880`014e7f52 48897e10 mov qword ptr [rsi+10h],rdi
fffff880`014e7f56 48897e18 mov qword ptr [rsi+18h],rdi
The problem seems (to me) that this instruction shud be:

48897e00 mov qword ptr [rsi+00h],rdi

Perhaps something wrong, not in IP, but the 32-bit word itself...
===============================================================================

Isolating:
---------
fffff880`014e7f4a 48 89 6e 20 mov qword ptr [rsi+20h],rbp <===< *****
fffff880`014e7f4a 48 89 7e 00 mov qword ptr [rsi+00h],rdi

Expanding more:
--------------
___6 ___e ___2 ___0 hex
0110 1110 0010 0000 bin

___7 ___e ___0 ___0 hex
0111 1110 0000 0000 bin
___^______ ^_____ <--- Specifically these bits: (2 to the 5th), (2 to the 12th)


Temporarily disregarding, of course:
Quote:
"IA processors are little endian machines..."
My System SpecsSystem Spec
.


18 Sep 2009   #14

Win7x64
 
 

Quote   Quote: Originally Posted by chuckr View Post
Quote:
fffff880`014e7f4a 48896e20 mov qword ptr [rsi+20h],rbp
fffff880`014e7f4e 48897e08 mov qword ptr [rsi+8],rdi
fffff880`014e7f52 48897e10 mov qword ptr [rsi+10h],rdi
fffff880`014e7f56 48897e18 mov qword ptr [rsi+18h],rdi
The IP seems to count OK:
No instruction at 4b may be because of correct IP increment,
(+1 per byte, viz):
4a = 48 89 6e 20
4b is the '89',
4c is the '6e',
4d is the '20',

then,
4e 48 89 7e 08 <---< is appropriate, count-wise.

What strikes me (as quick first look) is the "Increment" of the
"LOOP" or "REPx" instruction, not proceeding logically:
Starting at +00h, then bumping up by +08h.....

Quote:
Code:

0: kd> u fffff880`014e7f3a
ndis+0x1f3a:
fffff880`014e7f3a 8b6c2430 mov ebp,dword ptr [rsp+30h]
fffff880`014e7f3e 4885f6 test rsi,rsi
fffff880`014e7f41 0f8413840100 je ndis+0x1a35a (fffff880`0150035a)
fffff880`014e7f47 48893e mov qword ptr [rsi],rdi
fffff880`014e7f4a 48896e20 mov qword ptr [rsi+20h],rbp <===< *****
fffff880`014e7f4e 48897e08 mov qword ptr [rsi+8],rdi
fffff880`014e7f52 48897e10 mov qword ptr [rsi+10h],rdi
fffff880`014e7f56 48897e18 mov qword ptr [rsi+18h],rdi
The problem seems (to me) that this instruction shud be:

48897e00 mov qword ptr [rsi+00h],rdi

Perhaps something wrong, not in IP, but the 32-bit word itself...
Yep, just like DOS's "debug". Have rep

IDA has amazing graphical disassembly capabilities which are immensely useful when trying to understand other people's code - especially without access to "private" symbols. Between WinDBG/CDB/NTSD (all based on the same engine) and IDA, I haven't had any need to use another dedicated disassembler for a long time.

With regards to memtest and CPU stress test utils, I'm not well versed in those techniques. To me, the software's the interesting bit, and I'll happily defer to those with more knowledge when it comes to figuring out whether it's the third DIMM from the left or the APIC that's responsible for any given hardware weirdness.

As far as the IP is concerned, let's go a lot further back and start disassembly from there:

Code:
 
0: kd> u fffff880`014e7f10 L12
ndis+0x1f10:
fffff880`014e7f10 0041ff add byte ptr [rcx-1],al
fffff880`014e7f13 842c94 test byte ptr [rsp+rdx*4],ch
fffff880`014e7f16 0100 add dword ptr [rax],eax
fffff880`014e7f18 00ff add bh,bh
fffff880`014e7f1a 15b9310500 adc eax,531B9h
fffff880`014e7f1f 488bf0 mov rsi,rax
fffff880`014e7f22 4885c0 test rax,rax
fffff880`014e7f25 0f84aa010000 je ndis+0x20d5 (fffff880`014e80d5)
fffff880`014e7f2b 4885f6 test rsi,rsi
fffff880`014e7f2e 0f843a020000 je ndis+0x216e (fffff880`014e816e)
fffff880`014e7f34 448b642450 mov r12d,dword ptr [rsp+50h]
fffff880`014e7f39 4c8b6c2430 mov r13,qword ptr [rsp+30h]
fffff880`014e7f3e 4885f6 test rsi,rsi
fffff880`014e7f41 0f8413840100 je ndis+0x1a35a (fffff880`0150035a)
fffff880`014e7f47 48893e mov qword ptr [rsi],rdi
fffff880`014e7f4a 48896e20 mov qword ptr [rsi+20h],rbp
fffff880`014e7f4e 48897e08 mov qword ptr [rsi+8],rdi
fffff880`014e7f52 48897e10 mov qword ptr [rsi+10h],rdi
Going that far back, we can be almost certain that the disassembly has correctly "snapped to" by the time it reaches '4a. According to the in-memory version of the ndis.sys image, the instruction at '4a is 4 bytes long ("48896e20").

The problem with the IP is that it _should_ be at '4a or '4e, but certainly not '4b, because even if the in-memory NDIS image does not match the on-disk binary, the disassembly above shows the code that the machine ought to have been following.

Quote   Quote: Originally Posted by chuckr View Post
The problem seems (to me) that this instruction shud be:

48897e00 mov qword ptr [rsi+00h],rdi

Perhaps something wrong, not in IP, but the 32-bit word itself...
Quite possible. The in-memory image may be corrupted. We'd need somebody with a 7100 build (like the OP) to verify what's meant to be at that location. Bit-flips due to hardware issues may be responsible for both the IP misalignment and corruption of the binary image.

By itself, corruption of the in-memory image won't cause the IP to be misaligned though. However badly misrepresented the code may be in memory, perhaps due to software bugs, it's still meant to be precisely followed by the hardware, and the (R)IP should never be between two instructions.
My System SpecsSystem Spec
18 Sep 2009   #15

XP_Pro, W7_7201, W7RC.vhd, SciLinux5.3, Fedora12, Fedora9_2x, OpenSolaris_09-06
 
 

Quote:
The problem with the IP is that it _should_ be at '4a or '4e, but certainly not '4b, because even if the in-memory NDIS image does not match the on-disk binary, the disassembly above shows the code that the machine ought to have been following.
I believe the caveat here is:
Code:
Quote:
0: kd> .trap fffff880`031af4a0
NOTE: The trap frame does not contain all registers.
Some register values may be zeroed or incorrect.
rax=0000000000000008 rbx=0000000000000000 rcx=fffffa8004861b80
rdx=0000000000000001 rsi=0000000000000000 rdi=0000000000000000
rip=fffff880014e7f4b rsp=fffff880031af630 rbp=fffffa8004861a00
r8=0000000000000000 r9=0000000000000000 r10=fffffa8004861c00
r11=fffff880031af938 r12=0000000000000000 r13=0000000000000000
r14=0000000000000000 r15=0000000000000000
iopl=0 nv up ei pl nz na pe cy
ndis+0x1f4b:
fffff880`014e7f4b 896e20 mov dword ptr [rsi+20h],ebp ds:5c70:00000000`00000020=????????
Not knowing exactly how "real-time" the "trap-frame" operates, I would venture to guess that the possibility exists that:
the CPU 'instruction-decoder' was in the midst of updating the IP register
(which may only increment +1 at a time, depending upon hw logic gates),
other factors, other reasonings, etc. ("non-orthogonal" instruction set)

Note the instruction mnemonics:
Quote:
test rsi,rsi
je elsewhere >--> Heres where I "don't know" what TEST does, to satisfy the "GOTO"

mov [rsi],rdi ; 'Zero' start/dest indices seem correct, so reg_dump agrees
If I were a professional, I'd 'Instruction_Breakpoint' at 7f3e, then poke around the registers (during real-time execution).
Then 'Single-step' and poke around some more.
Maybe setting a 'Data_Breakpoint' or two, at curious areas.

Quote:
By itself, corruption of the in-memory image won't cause the IP to be misaligned though. However badly misrepresented the code may be in memory, perhaps due to software bugs, it's still meant to be precisely followed by the hardware, and the (R)IP should never be between two instructions.
That's where I would think differently:
the 'non-orthogonal' instruction set and the 'instruction-decoder' could well change the IP register with screwy counts:
Immediately to mind would be this fake example:
Opcode 0x40 = Load Accumulator with register C (maybe 2 bytes, immed)
Opcode 0x41 = Load Acc from Memory location 0x1cad (6 bytes?)
A one-bit change, interpreted by the 'instruction-decoder', would delta the IP by +/- 4 more/less than intended.

Debug of the (good) .exe may not show this on the 2nd load, because only the 1st load (real-time run) exhibited the error.

Surely, there exists a hw problem.... If I were a betting man, the CPU!

Isolation requires in-person 'hand-holding', observation, and trusty 'tools'...

Thanks for the discussion - Gotta fire up the barbie now...

Chuck

Hope we don't both get the BanHammer, for getting this thread:
My System SpecsSystem Spec
18 Sep 2009   #16

Win7x64
 
 

Endian little hate I

Couldn't help myself - I had to hunt down a 7100 machine like the OPs and check that range. The NDIS.SYS in-memory image is intact in their case, at least in that location:

Mine:
.text:0000000000011F40 F6 0F 84 13 84 01 00 48 89 3E 48 89 6E 20 48 89 .H>Hn H

OPs:
0: kd> db fffff880`014e7f40 L10
fffff880`014e7f40 f6 0f 84 13 84 01 00 48-89 3e 48 89 6e 20 48 89 .......H.>H.n H.

I used WinDBG for the OPs and IDA for mine, just to confirm. Unsurprisingly, they agree on the disassembly. Perhaps the reference to RSI+20h and RBP is located there for pipelining reasons - some sort of structural or data hazard avoidance.
My System SpecsSystem Spec
18 Sep 2009   #17

XP_Pro, W7_7201, W7RC.vhd, SciLinux5.3, Fedora12, Fedora9_2x, OpenSolaris_09-06
 
 

Quote   Quote: Originally Posted by H2SO4 View Post
Endian little hate I

Couldn't help myself - I had to hunt down a 7100 machine like the OPs and check that range.
t_em
!.oo

But I'm gonna hit the 'Off' switch and read your post at Coffee-time...

You really don't know what the OP has...
You're assuming a valid, operable 7100, like you have...

Ta.
My System SpecsSystem Spec
18 Sep 2009   #18

Win7x64
 
 

Thanks for a very interesting discussion

Quote:
You really don't know what the OP has...
You're assuming a valid, operable 7100, like you have...
The aim was to check whether their in-memory version of the instruction at '4a matches ndis.sys on another 7100 box, or whether it was possibly mangled as you suspected (and I agree there was good reason to suspect that). Their minidump tells me some details regarding the OS version labelling and the specifics of their NDIS.SYS binary ('vertarget', '!lmi ndis.sys'), and the comparison to my own (presumed good) copy tells me that there is no discrepancy, at least in that area - the '4a instruction really is "mov [rsi+20h], rbp".

Quote:
I believe the caveat here is:

Quote:
0: kd> .trap fffff880`031af4a0
NOTE: The trap frame does not contain all registers.
Some register values may be zeroed or incorrect.
The Windows trap frame struct ('dt _KTRAP_FRAME') doesn't necessarily get populated with the contents of every register - only those which are necessary for the operation of a particular type of trap handler: nt!KiTrap0E, nt!KiTrap0A... Hence, the warning above is spewed by the debugger as a generic reminder that at least some of the values may not be accurate. (R)IP is obviously essential though - so we can get back to where we left off when the handler's done - and it'll absolutely be saved every time. In the OPs case, the RIP value is undeniably populated and pointing close to where it should, albeit off-by-one byte:

0: kd> dt _KTRAP_FRAME fffff880`031af4a0 RIP
nt!_KTRAP_FRAME
+0x168 Rip : 0xfffff880`014e7f4b

(That's where the debugger gets its own 'kv' trap info of course.)

Quote:
Not knowing exactly how "real-time" the "trap-frame" operates, I would venture to guess that the possibility exists that:
the CPU 'instruction-decoder' was in the midst of updating the IP register
(which may only increment +1 at a time, depending upon hw logic gates),
For what it's worth, I don't believe it works that way. From a software point of view, IP updates are an atomic operation, and the OS will never be able to watch the IP "count" incrementally between two valid instruction offsets.
Quote:
If I were a professional, I'd 'Instruction_Breakpoint' at 7f3e, then poke around the registers (during real-time execution).
Then 'Single-step' and poke around some more.
Maybe setting a 'Data_Breakpoint' or two, at curious areas.
Without wishing to be seen to be buttering up a forum heavyweight, it's very obvious that you're very professional

I agree completely that if we had a setup with a reproducible fault and a kernel debugger hooked up it would be very interesting to 'bp <\'7f3e>', then 't' for a bit, watch if it's going to branch or not in that conditional jump, and 'ba <address>' (hardware breakpoint) on some of the underlying structures. I rather doubt this is reproducible though - if it's hardware, it may never happen again in the same way and in the same place.
Quote:
That's where I would think differently:
the 'non-orthogonal' instruction set and the 'instruction-decoder' could well change the IP register with screwy counts:
Oh sure, software can directly walk the IP all over the place (the debugger does it all the time), but the point is that the code in question does nothing to directly shunt the IP one byte further along than it should be. Perhaps the thread was pre-empted and its context record was damaged, but the chances are very small that the stored RIP value merely got INCed (or similar).
Quote:
Surely, there exists a hw problem.... If I were a betting man, the CPU!

Isolation requires in-person 'hand-holding', observation, and trusty 'tools'...
Yes, I certainly wouldn't be putting my money on a software flaw in this particular crash. I don't know whether it's the processor though.
Quote:
Hope we don't both get the BanHammer, for getting this thread:
I'm prepared to run that risk for the joy I get from discussing these issues
My System SpecsSystem Spec
20 Sep 2009   #19

XP_Pro, W7_7201, W7RC.vhd, SciLinux5.3, Fedora12, Fedora9_2x, OpenSolaris_09-06
 
 
H2S04 1's and 0's



Didn't want this thing to 'die on the vine', especially since you went through the trouble of verifying the binary file 'ndis.sys'.

Obviously, the OP has the correct code with his ndis.sys and the debug dump also indicates that.

My aiming at the instruction: mov qword ptr [rsi+20h],rbp
was definitely with blinders on, assuming the +08h should have been in an orderly 'progression', starting with +00h.

The bloody +00h is, in fact there, simply not indicated as such.
The TEST and JE mnemonics I've kissed off as checking for 'in bounds' exceptions.

Quote:
0: kd> u fffff880`014e7f10 L12
ndis+0x1f10:

014e7f10 0041ff add byte ptr [rcx-1],al
014e7f13 842c94 test byte ptr [rsp+rdx*4],ch
014e7f16 0100 add dword ptr [rax],eax
014e7f18 00ff add bh,bh
014e7f1a 15 b9310500 adc eax,531B9h
014e7f1f 488b f0________ mov rsi,rax

014e7f22 4885 c0________ test rax,rax
014e7f25 0f84 aa010000__ je ndis+0x20d5 (014e80d5)

014e7f2b 4885 f6________ test rsi,rsi
014e7f2e 0f84 3a020000 je ndis+0x216e (014e816e)

014e7f34 448b642450_____ mov r12d,dword ptr [rsp+50h]
014e7f39 4c8b6c2430_____ mov r13,qword ptr [rsp+30h]

014e7f3e 4885 f6________ test rsi,rsi
014e7f41 0f84 13840100__ je ndis+0x1a35a (0150035a)

014e7f47 4889 3e________ mov qword ptr [rsi],rdi <===< mov qword ptr [rsi+00h],rdi
014e7f4a 4889 6e 20_____ mov qword ptr [rsi+20h],rbp
014e7f4e 4889 7e 08_____ mov qword ptr [rsi+8],rdi
014e7f52 4889 7e 10_____ mov qword ptr [rsi+10h],rdi
These are excerpts from the Intel IA-32 manual, but might be similar for x64:

Quote:
TEST — Logical Compare

Description:
This instruction computes the bit-wise logical AND of first operand (source 1 operand) and the
second operand (source 2 operand) and sets the SF, ZF, and PF status flags according to the
result. The result is then discarded.

Operation: (in Pseudo c code)
TEMP SRC1 AND SRC2;
SF MSB(TEMP);
IF TEMP = 0
THEN ZF 1;
ELSE ZF 0;
FI:
PF BitwiseXNOR(TEMP[0:7]);
CF 0;
OF 0;
(*AF is Undefined*)

Flags Affected:
The OF and CF flags are cleared to 0.
The SF, ZF, and PF flags are set according to the result
(refer to the “Operation” section above). The state of the AF flag is undefined.

Protected Mode Exceptions:
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or
GS segment limit.
If the DS, ES, FS, or GS register contains a null segment selector.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory reference is
made while the current privilege level is 3.

Real-Address Mode Exceptions:
#GP If a memory operand effective address is outside the CS, DS, ES, FS, or
GS segment limit.
#SS If a memory operand effective address is outside the SS segment limit.

Virtual-8086 Mode Exceptions:
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or
GS segment limit.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory reference is
made.
----------------------------------------------------
Jcc — Jump if Condition Is Met (Continued)

Opcode Instruction Description

0F 84 cw/cd JE rel16/32 Jump near if equal (ZF=1)

This instruction checks the state of one or more of the status flags in the EFLAGS register (CF,
OF, PF, SF, and ZF) and, if the flags are in the specified state (condition), performs a jump to the
target instruction specified by the destination operand. A condition code (cc) is associated with
each instruction to indicate the condition being tested for. If the condition is not satisfied, the
jump is not performed and execution continues with the instruction following the Jcc instruction.
Is it 'normal' for 64-bit code to be using Dword pointers?

Does your 7100 with that ndis.sys operate correctly?

Since you like this stuff, is there any way that you could execute this "chunk" of code under 'controlled' circumstances?
My System SpecsSystem Spec
20 Sep 2009   #20

Win7x64
 
 

Quote   Quote: Originally Posted by chuckr View Post
Didn't want this thing to 'die on the vine', especially since you went through the trouble of verifying the binary file 'ndis.sys'. Obviously, the OP has the correct code with his ndis.sys and the debug dump also indicates that.
Glad to talk about it any time

In reality I only verified the contents of the QWord starting at 0xfffff880`014e7f40 - the one that contains the '4a and '4e instructions, as well as the (non-existent) '4b instruction the box seemingly tried to execute at the time of the crash. I cannot be certain whether the OPs entire NDIS.SYS image is correct, mostly because it's not all recorded in the 270KB worth of minidump! (If we had a full kernel dump from the OP we could use the debugger's !chkimg extension to verify the whole thing against a known-good copy.)

Quote   Quote: Originally Posted by chuckr View Post
My aiming at the instruction: mov qword ptr [rsi+20h],rbp
was definitely with blinders on, assuming the +08h should have been in an orderly 'progression', starting with +00h. The bloody +00h is, in fact there, simply not indicated as such.
Sure, "[rsi]" is equivalent to "[rsi+00h]", if that's what you mean. That's just the way WinDBG chooses to present the disassembled mnemonics.

Quote   Quote: Originally Posted by chuckr View Post
Is it 'normal' for 64-bit code to be using Dword pointers?
I don't think I understand where you're seeing the 32-bit pointer(s)? They certainly shouldn't be any absolute 32-bit pointers because a jump to such an address would easily take us out of the kernel-mode address space on an x64/IA-64 machine and thereby cause a crash.

There's nothing wrong with 32-bit relative displacement though. Perhaps you're referring to this?

...
fffff880`014e7f3e 4885f6 test rsi,rsi
fffff880`014e7f41 0f8413840100 je ndis+0x1a35a (fffff880`0150035a)
fffff880`014e7f47 48893e mov qword ptr [rsi],rdi
...

That conditional jump at '41 uses a relative offset - relative to the current position. As per the Intel doc you quoted, the 'je' instruction includes a relative ("rel") 16/32-bit pointer:

Quote:
0F 84 cw/cd JE rel16/32 Jump near if equal (ZF=1).
In the OP's case, the entire instruction is "0f8413840100". Hence, the leading "0f84" is the opcode and "13840100" is the relative offset in little-endian, so 0x18413 to me and you.

The starting point for that displacement is the IP as it would have looked after the jump instruction is fetched (note the atomic nature of the IP update):

fffff880`014e7f41 0f8413840100 je ndis+0x1a35a (fffff880`0150035a)
fffff880`014e7f47 48893e mov qword ptr [rsi],rdi

Adding the 'je' instruction's relative displacement to the IP yields:

0: kd> ? fffff880`014e7f47 + 0x18413
Evaluate expression: -8246315187366 = fffff880`0150035a

Let's now get the load address of NDIS.SYS as a starting point...

0: kd> lmm ndis
start end module name
fffff880`014e6000 fffff880`015d7000 ndis T (no symbols)

If we compare the displacement between the jump's destination and the NDIS load address:

0: kd> ? fffff880`0150035a - fffff880`014e6000
Evaluate expression: 107354 = 00000000`0001a35a

So the final jump destination would be NDIS+0x1a35a, as per WinDBG's calculation highlighted in pink up higher above. To me, it all seems to check out.

Quote   Quote: Originally Posted by chuckr View Post
Does your 7100 with that ndis.sys operate correctly?
Yes, to the best of my knowledge. It certainly doesn't BSOD.

Quote   Quote: Originally Posted by chuckr View Post
Since you like this stuff, is there any way that you could execute this "chunk" of code under 'controlled' circumstances?
Sure, no problem. I can run it under a kernel debugger and thus control its operation. If you like, you can drive. Let me know what breakpoints you'd like set and I'll paste back the results. Good geeky fun
My System SpecsSystem Spec
Reply

 Recurring BSOD Problem




Thread Tools



Similar help and support threads for2: Recurring BSOD Problem
Thread Forum
File name too long recurring big problem General Discussion
Recurring problem with dowloading anything in Windows 7 Browsers & Mail
Recurring Problem I have noticed with connecting to two networks Network & Sharing
BSODs with different error messages, problem recurring! BSOD Help and Support
Recurring Problem with Updates Windows Updates & Activation
Recurring BSOD BSOD Help and Support
Recurring Problem BSOD Help and Support

Our Sites

Site Links

About Us

Find Us

Windows 7 Forums is an independent web site and has not been authorized, sponsored, or otherwise approved by Microsoft Corporation. "Windows 7" and related materials are trademarks of Microsoft Corp.

Designer Media Ltd

All times are GMT -5. The time now is 06:31 PM.
Twitter Facebook Google+



Windows 7 Forums

Seven Forums Android App Seven Forums IOS App
  

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33