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Windows 7: Micron's ClearNAND: 25nm + ECC, Combats Increasing Error Rates


01 Feb 2011   #1

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Windows 7 Ult x64 - SP1/ Windows 8 Pro x64
 
 
Micron's ClearNAND: 25nm + ECC, Combats Increasing Error Rates

I guess smaller is not always better.

This is what's causing the delay of the Gen3 SSDs.
All G3 SSDs are having these issues, it's due to the 25nm nand memory has more errors and wears out faster than the previous larger sizes. This is mainly due to it being so much smaller.
Read below for the details.

Hope they can find a resolution for this issue.

Micron's ClearNAND: 25nm + ECC, Combats Increasing Error Rates


Quote:
Eleven months ago Intel and Micron, jointly as IMFT,announced intentions to move to 25nm NAND by the end of 2010. For the past few months, IMFT has been shipping 25nm NAND although none of it has ended up in the high performance SSDs we love to cover just yet.
The problem, as with a jump to any new manufacturing node, has to do with yields. In the microprocessor space, new processes generally mean you can’t reach your clock targets and you may use more power than you’d like. The more experience you have in working with the process the more you can get these two variables under control and eventually you have a technology you can ship to the market.

The same is true with NAND, although the vectors of improvement are a bit different. Rather than clock speed and power (although both are affected) the main focus these past few months has been increasing endurance and reducing uncorrectable bit error rate.

When I first started reviewing SSDs IMFT was shipping 50nm MLC NAND rated at 10,000 program/erase cycles per cell. As I mentioned in a recent SSD article, the move to 3xnm cut that endurance rating in half. Current NAND shipping in SSDs can only last half as long, or approximately 5,000 program/erase cycles per cell. Things aren’t looking any better for 25nm. Although the first 25nm MLC test parts could only manage 1,000 P/E cycles, today 25nm MLC NAND is good for around 3,000 program/erase cycles per cell.
The reduction in P/E cycles is directly related to the physics of shrinking these NAND cells; the smaller they get, the faster they deteriorate with each write. Remember this diagram?
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 Micron's ClearNAND: 25nm + ECC, Combats Increasing Error Rates




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