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I wonder when the modules hit the consumer market how much of a premium over DDR3 they'll be?
Read more at:What's the future of memory look like? NAND flash? Hybrid memory cubes? The memory makers over at Micron have their hands in both of those technologies, but they're also banking on a third form hitting the streets before too long, bearing a striking resemblance to the DDR3 we all know and love. This weekend, the company announced that "its first fully functional DDR4 DRAM module" is up and running and should make it to market in 2013.
Maximum PC | Adios, DDR3: Micron Says Its DDR4 DRAM Modules Are Coming In 2013
I wonder when the modules hit the consumer market how much of a premium over DDR3 they'll be?
The final specs should be approved in a few Months and then we can get a look at the speed. I believe they will run at 1.2v and have CRC for the data which is only available in ECC memory now. Then the CPU's will need a reworked memory controller. I'm in no rush but its always nice to have better technologies when I get ready for my next build. My new builds usually include new MB, CPU, Memory. I use the Intel process. I don't do Ticks (small improvements) I do Tocks (new technologies).
Jim
Will it matter?
IBM has been working on a new memory technology that's supposed to make DDR3 look like the old wire and donut matrix of the 60s and 70s. Something like in the multi-Ghz clock speed with transfer rates measured in TB/s. I could see this eliminating processor prefetch and L3 cache. The processor issues a read and the data is there!
There is always research going on for new technologies. First they have to get it working in the lab and then make it affordable. They are a lot of great technologies that never made it out of the lab because it was not economical to produce. Its all about the money and what they can actually sell.
Jim
Agree, but that's what they said about the transistor in the 50s--It would be too expensive to produce. Todays processors have Billions on a single chip.
Because the memory could possibly be faster than the processor for one. The processor would issue a read and the next step has the data. L1, L2 and L3 cache is the processor's "prefetch" memory.Why should this eliminate prefetch.
I think you're confusing processor cache with disk (OS) to memory prefetch buffering. Mostly my fault but I thought we were talking about memory technology. Disk prefetch would still be needed and still remain the bottleneck.