Need help with overclocking basics

Hi members,

I need some help to understand the basics of overclocking. I dont really know where to start, i'll try to be has clear as possible.
On some post David asks:

Should the DDR2 memory DRAM Frequency be as close to the Bus Speed of the CPU as possible?

David specs:

DRAM Frequency - 301.1 MHz
FSB : RAM - 2:3
CL, tRCD, tRP - all 4 clocks
Cycle Time - 12 clocks
Core Speed 3010.8 MHz
Multiplier - x15.0
Bus Speed - 200.7 MHz
FSB - 802.9

Then paul explain that we should consider the real transfer rate in mb/s of both the memory and the processor bandwidth to match.

Paul calculs:

if you had dual channel memory at PC2-4800 (which is DDR2-600 rate),
the bandwidth might look like 2*4800 = 9600MB/sec
The processor is 8 * FSB800 = 6400MB/sec.

The first calcul is 4800 * 2 because its in dual channel thats ok.. But on the processor one (8 * FSB800) where does the 8 come from?

I also have some other question about this after someone kindly help me get this clear.

With google, i have some progress:

8 counts as the amount of "bits" per data cycle.

Before i can understand this, there comes another question: How can i know how many transfers per Clock Cycle my cpu can do?

Number of cores 2 (max 2)
Number of threads 2 (max 2)
Name AMD Athlon 64 X2 5200+
Codename Windsor
Specification AMD Athlon(tm) 64 X2 Dual Core Processor 5200+
Package Socket AM2 (940)
CPUID F.3.2
Extended CPUID F.43
Brand ID 4
Core Stepping JH-F2
Technology 90 nm
Core Speed 2612.2 MHz
Multiplier x FSB 13.0 x 200.9 MHz
HT Link speed 1004.7 MHz
Stock frequency 2600 MHz
Instructions sets MMX (+), 3DNow! (+), SSE, SSE2, SSE3, x86-64, AMD-V
L1 Data cache 2 x 64 KBytes, 2-way set associative, 64-byte line size
L1 Instruction cache 2 x 64 KBytes, 2-way set associative, 64-byte line size
L2 cache 2 x 1024 KBytes, 16-way set associative, 64-byte line size
FID/VID Control yes
Max FID 13.0x
Max VID 1.350 V

Im not talking about a specific manufacturer but in general. As i said i try to as clear as possible.

Also, i'v found something about the "transfers per clock cycle"

Let's say a cpu operates at 8MHz. That means it breaks down time into little units per second. The number of units per second in this case is 8 million (1 MHz = 1 million Hz). The CPU sees "time" as being 8 million units per second, with each unit being a clock cycle.

The amount of data that can be sent by a bus per clock cycle is the bus width - If a bus width is 16-bit. On each clock cycle, 16 bits of data are sent, or received, depending.

So if i understand correctly, this cpu would transfert (8 000 000 * 16) 128 000 000 bits in a second?

128000000 bits = 16000000 byte = 15.25 mb/s

That doesnt make any sense 15.25 mb/s is way too much for a 8 mhz cpu !?

I see what im missing:

Assume that this microprocessor has a bus cycle whose minimum duration equals four input clock cycles.

The info we really need is the external bus width (16-bit), the CPU clock speed (8MHz), and the fact that the external bus clock cycle is 1/4 the speed of the CPU.
So the bandwidth of the external bus (often called the FSB or Front-Side Bus in today's CPU's) is the width times the speed. The width is 16-bit, the speed is 1/4 of 8MHz = 2MHz

Here is the complete thread

It takes a minimum of 4 internal bus clock cycle to do a "transfer"
The internal bus clock cycle beeing 8 mhz in this case (8 million units per second)

Am i right?

Thank's guys for your answers i appreciate. I guess the title should have been "Need help with computer architecture basics". I guess i had in mind to overclock my old pc while really knowing what i was doiing. So i had to understand a few things.

Is it too late to keep goiing with the "Data Transfers per Clock Cycle"?

Not all processors will use a "Four Data Transfers per Clock Cycle" system. The old Athlon XP only used a dual (2) system.

Where is it possible to find this info about any cpu?