TEST — Logical Compare
Description:
This instruction computes the bit-wise logical AND of first operand (source 1 operand) and the
second operand (source 2 operand) and sets the SF, ZF, and PF status flags according to the
result. The result is then discarded.
Operation: (in Pseudo c code)
TEMP ¬ SRC1 AND SRC2;
SF ¬ MSB(TEMP);
IF TEMP = 0
THEN ZF ¬ 1;
ELSE ZF ¬ 0;
FI:
PF ¬ BitwiseXNOR(TEMP[0:7]);
CF ¬ 0;
OF ¬ 0;
(*AF is Undefined*)
Flags Affected:
The OF and CF flags are cleared to 0.
The SF, ZF, and PF flags are set according to the result
(refer to the “Operation” section above). The state of the AF flag is undefined.
Protected Mode Exceptions:
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or
GS segment limit.
If the DS, ES, FS, or GS register contains a null segment selector.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory reference is
made while the current privilege level is 3.
Real-Address Mode Exceptions:
#GP If a memory operand effective address is outside the CS, DS, ES, FS, or
GS segment limit.
#SS If a memory operand effective address is outside the SS segment limit.
Virtual-8086 Mode Exceptions:
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or
GS segment limit.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory reference is
made.
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Jcc — Jump if Condition Is Met (Continued)
Opcode Instruction Description
0F 84 cw/cd JE rel16/32 Jump near if equal (ZF=1)
This instruction checks the state of one or more of the status flags in the EFLAGS register (CF,
OF, PF, SF, and ZF) and, if the flags are in the specified state (condition), performs a jump to the
target instruction specified by the destination operand. A condition code (cc) is associated with
each instruction to indicate the condition being tested for. If the condition is not satisfied, the
jump is not performed and execution continues with the instruction following the Jcc instruction.