AMD back in the game with impressive Shanghai debut!

Almost one year to the day after Phenom debuted on the desktop and fell flat on its face, AMD is back with its 45nm Shanghai refresh. Calling this processor launch "important" would be a colossal understatement; AMD's ability to continue as a going concern in the x86 market fundamentally depends on how well Shanghai performs. AMD has spent the last twelve months rather pointedly not talking about Shanghai; the only topic it discussed less was asset smart.

AMD hasn't revealed all the details on what it revamped in Shanghai, but here's what we know. Shanghai is 65nm Barcelona respun on 45nm technology. It carries 6MB of L3 (up from 2MB), and it will officially support DDR2-800 (Barcelona topped out at DDR2-667). AMD has added support for a power-saving technology it calls Smart Fetch (we'll discuss that in a moment), and improved virtualization performance. The processor's integrated memory controller also got a few upgrades, and can now split itself into two 64-bit channels, as opposed to always being stuck in 128-bit mode. Doing so allows the processor to perform simultaneous read/writes, though maximum bandwidth through either channel is obviously just half of the standard total. AMD also improved how frequently Shanghai can query CPUs in other sockets—if I've understood correctly, this is only useful to companies deploying two-socket solutions and up.

Fetch, Shanghai, fetch.

Smart Fetch is AMD's new power-saving technology that allows the chip to completely power down cores that aren't in use. No word yet on whether or not this feature will make it into Deneb, the upcoming desktop flavor of Shanghai, but I'd bet it will, probably as part of a revamped "Super Cool'n'Quiet Deluxe Extreme WTF Edition, now with Silicon-on-Peanut-Butter technology." AMD is touting Smart Fetch as an example of why an exclusionary cache design, in which L1/L2 aren't duplicated in L3, is better than an inclusive cache hierarchy, in which L1/L2 data is duplicated in L3. Intel's cache structure is inclusive, AMD's is exclusive, and the two of them have been fighting over which is better since K7 debuted in 1999. We'll let them argue over it, and look at smart Fetch instead.
Smart Fetch kicks in when a Shanghai core is ready for beddy-bye. Instead of dropping the CPU into a sleep state, Smart Fetch reads the sum totals of its L1 and L2 cache, then drops that data into L3, presumably flagging it in a way that tells the other cores not to write data into those blocks. The appropriate core is then powered off completely, which saves power. When the processor needs the core to power up again, Smart Fetch hurries off, grabs the requisite blocks of L3 cache, and rewrites them into L1/L2.

Read more at the source.


Later Ted

Posted By: Bare Foot Kid
13 Nov 2008