3.4 Main Memory Address Space (4 GB to TOUUD)
The MCH supports 36 bit addressing. The maximum main memory size supported is 8 GB total DRAM memory. A hole between TOLUD and 4 GB occurs when main memory size approaches 4 GB or larger. As a result, TOM, and TOUUD registers and RECLAIMBASE/RECLAIMLIMIT registers become relevant.
The new reclaim configuration registers exist to reclaim lost main memory space. The greater than 32 bit reclaim handling will be handled similar to other MCHs.
Upstream read and write accesses above 36-bit addressing will be treated as invalid cycles by PCI Express and DMI.
Top of Memory
The “Top of Memory” (TOM) register reflects the total amount of populated physical memory. This is NOT necessarily the highest main memory address (holes may exist in main memory address map due to addresses allocated for memory-mapped I/O above TOM). TOM is used to allocate the Intel Management Engine's stolen memory.
The Intel
ME stolen size register reflects the total amount of physical memory stolen by the Intel ME. The ME stolen memory is located at the top of physical memory. The ME stolen memory base is calculated by subtracting the amount of memory stolen by the Intel ME from TOM.
The Top of Upper Usable Dram (TOUUD) register reflects the total amount of addressable DRAM. If reclaim is disabled, TOUUD will reflect TOM minus Intel ME stolen
size. If reclaim is enabled, then it will reflect the reclaim limit. Also, the reclaim base will be the same as TOM minus ME stolen memory size to the nearest 64 MB alignment.
TOLUD register is restricted to 4 GB memory (A[31:20]), but the MCH can support up to 16 GB, limited by DRAM pins. For physical memory greater than 4 GB, the TOUUD
register helps identify the address range in between the 4 GB boundary and the top of physical memory. This identifies memory that can be directly accessed (including
reclaim address calculation) which is useful for memory access indication, early path indication, and trusted read indication. When reclaim is enabled, TOLUD must be
64 MB aligned, but when reclaim is disabled, TOLUD can be 1 MB aligned.
C1DRB3 cannot be used directly to determine the effective size of memory as the values programmed in the DRBs depend on the memory mode (stacked, interleaved).
The Reclaim Base/Limit registers also can not be used because reclaim can be disabled.
The C0DRB3 register is used for memory channel identification (channel 0 vs. channel 1) in the case of stacked memory.
Datasheet 45
System Address Map
3.4.1 Memory Re-claim Background
The following are examples of Memory Mapped IO devices are typically located below
4 GB:
• High BIOS
• HSEG
• TSEG
• XAPIC
• Local APIC
• FSB Interrupts
• Mbase/Mlimit
• Memory Mapped IO space that supports only 32 B addressing
The MCH provides the capability to re-claim the physical memory overlapped by the Memory Mapped I/O logical address space. The MCH re-maps physical memory from
the Top of Low Memory (TOLUD) boundary up to the 4 GB boundary to an equivalent sized logical address range located just below the Intel ME's stolen memory.
3.4.2 Memory Reclaiming
An incoming address (referred to as a logical address) is checked to see if it falls in the memory re-map window. The bottom of the re-map window is defined by the value in the RECLAIMBASE register. The top of the re-map window is defined by the value in the
RECLAIMLIMIT register. An address that falls within this window is reclaimed to the physical memory starting at the address defined by the TOLUD register. The TOLUD
register must be 64M aligned when RECLAIM is enabled, but can be 1M aligned when reclaim is disabled.
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